ALTLVDS IP: Can serdes channels be placed into different IO banks?

I am using CycloneV SEBA4 device and implementing a design with ALTLVDS_TX and RX IPs with 5 channels. I am using IOBanks 4A,3B and 5A with PLL of bank 4A with IP internal PLL settings. All channels are identical and "analysis & synthesis" is successful, but fitter generates error 175020 for one TX channel, which is placed in bank 3B(DIFFIO_TX pin). I have compiled the design on quartus 15.0 and 15.1 both, and received the same error.

I have used this solution :- https://www.altera.com/support/support-resources/knowledge-base/solutions/fb78288.html

I get the critical warning of PLL not being in LVDS mode, as suggested in the solution. But still fitter generates error. Kindly suggest a probable cause and workaround for this error.

Complete error is shown below

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)).

Error (175020): The Fitter cannot place logic pin in region (9, 0) to (22, 0), to which it is constrained, because there are no valid locations in the region for logic of this type.

Info (14596): Information about the failing component(s):

Info (175028): The pin name(s): lvds_tx_master_0_lvds_out_lvds_tx[3]

Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:

Info (175015): The I/O pad lvds_tx_master_0_lvds_out_lvds_tx[3] is constrained to the location PIN_AE7 due to: User Location Constraints (PIN_AE7)

Info (14709): The constrained I/O pad is contained within this pin

Error (175010): Location failed detailed legality checks (1 location affected)

Info (175029): pin containing PIN_AE7