ALTLVDS and Cyclone IV E maximum data rate and PLL frequency

LVDS signals are send and received by DDR registers, using a clock of half bit rate. Thus 840MBPS can work with available Cyclone clock speed. You should consider however, that the window for correct data receiption is rather small at 840 MHz. Unlike Stratix and Arria family devices, Cyclone has no means to adjust the receive clock to compensate for data skew. So you should check thoroughly, if 840 MBPS will work reliably for your application. Choosing a slightly lower bit rate will things much easier, if possible.