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you should only moniter the signals on the side of the FIFO you are looking at, you should never anticipate when data will be ready.
On the write side of the fifo, you can keep writing on every clock cycle until it is full (and you can set a nearly full threshold to help you control). and on the read side you can keep reading until it is empty.
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Hi,
To read fast and simple from the fifo( do this with underflow protection and show ahead ON):
When read_state =>
Read<='1';
if read='1' and empty='0' then
....
if (done_condition_variable='1') then
read<='0';
state<=other_state:
end if;
end if:
Honored Contributor
