Altera Agilex PCIe core

Hi nalingam, 

Apologies for the late reply. 

You can check the following: 

• p<n>_initiate_warmrst_req is an output from the IP to the user reset controller. For the PERST#-triggered cold-reset path, cold reset is initiated by deassertion of p<n>_pin_perst_n_i (PERST# released: low → high). The IP then asserts p<n>_initiate_warmrst_req, and your controller should respond with p<n>_subsystem_rst_req. 
• For a user-initiated cold reset, start by asserting p<n>_subsystem_rst_req. In that flow, initiate_warmrst_req is not the trigger and is not required. 
• Before PERST# deassertion in simulation, ensure ninit_done is 0 (device configured). 
• Compare your reset controller and PERST# timing against the design example generated in Quartus Prime for this IP. Refer to the following Design Example user guide for the steps to generate a Design Example: https://docs.altera.com/r/docs/817713/25.3/gts-axi-streaming-ip-for-pci-express-design-example-user-guide/about-the-gts-axi-streaming-ip-for-pci-express-design-example

Thanks. 

Best Regards, 

Ven