ymiler
Contributor
ContributorALM structure
Hi
I implemented AND gate and sample it by FF :
Code :
wire b,c ;
reg a_sam;
always @(posedge clk)
a_sam <= b && c;
When the Fitter (finalize) step is finised I opened...
Forum Discussion
FvM
Super Contributor
Super ContributorHello,
the doubled LUT makes no sense at first sight. The effect is, that logic output is the same for both selector states. One would expect that the result can be achieved easier.
Which FPGA family are we seeing here?
the doubled LUT makes no sense at first sight. The effect is, that logic output is the same for both selector states. One would expect that the result can be achieved easier.
Which FPGA family are we seeing here?
- ymiler
Quartus Prime version 22.3
Device Family Stratix 10
Device 1SM21BHU2F53E2VG
