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ymiler's avatar
ymiler
Icon for Contributor rankContributor
3 years ago

ALM structure

Hi I implemented AND gate and sample it by FF : Code : wire b,c ; reg a_sam; always @(posedge clk) a_sam <= b && c; When the Fitter (finalize) step is finised I opened...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Check the links below where ALM operated in Normal Mode:

https://www.intel.com/content/www/us/en/docs/programmable/683775/current/normal-mode.html

https://www.intel.com/content/www/us/en/docs/programmable/683699/current/normal-mode.html

Note: The Quartus® Prime Pro Edition Compiler automatically selects the inputs to the LUT. ALMs in normal mode support register packing.

The LUT Equation also varies with MLAB cell location and device type.


Thanks,

Best Regards,

Sheng


ymiler's avatar
ymiler
Icon for Contributor rankContributor
3 years ago

OK

But , Why Quartus use 2 LUT's to implement simple "AND" gate ? how does MUX beaviour ? What is the "select" value ?

Yishay