ymiler
Contributor
ContributorALM structure
Hi
I implemented AND gate and sample it by FF :
Code :
wire b,c ;
reg a_sam;
always @(posedge clk)
a_sam <= b && c;
When the Fitter (finalize) step is finised I opened...
Forum Discussion
ymilerContributor
ContributorHi Sheng,
Thanks for you reply ,
Now I'm understanding the mask formula .
But , the code was :
always @(posedge clk)
a_sam <= b && c;
Why do the equation defined as : !a & !d - I didnt write "not" to theses wires ?
In addition ,
Why Quartus use 2 LUT's to implement simple "AND" gate ? how does MUX beaviour ? What is the "select" value ?
