ymiler
Contributor
ContributorALM structure
Hi
I implemented AND gate and sample it by FF :
Code :
wire b,c ;
reg a_sam;
always @(posedge clk)
a_sam <= b && c;
When the Fitter (finalize) step is finised I opened...
Forum Discussion
ShengN_altera
Super Contributor
Super ContributorHi,
F0 and F1 are lookup table (LUT). A lookup table (LUT) that implements an arbitrary Boolean function of N inputs is often referred to as an N-LUT check this document https://www.intel.com/content/www/us/en/docs/programmable/683152/22-4/lookup-table-lut.html.
Based on the truth table of the LUT's function http://www2.informatik.uni-freiburg.de/~feiten/teaching/floorplan_ex/tutorial_3.htm, with the LUT Equation !a & !d you'll get LUT Mask of 0000 0000 0101 0101 (0055).
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
