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PAA's avatar
PAA
Icon for New Contributor rankNew Contributor
2 years ago

Agilex5 mipi phy IP configuration issue

We are attempting to test CSI IP on Agilex5 on AXE5-Eagle Arrow Development board, and find that the byte Location assignments on the mipi phy seems to have bug, as it does not allow us to use odd by...
Video
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Pushpraj,

Thanks for your reply and clear picture clarification, Please allow me to have sometime to check on the error that you seeing.
To ensure that we are looking at the same picture, is it possible to attach the error design .qar in here ?
So that I am not looking at different setup.

Regards,
Wincent_Intel

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Pushpraj,

Upon check with our internal development team.

  • The GUI display you see on Link x tab -> link x location,
  • it can only display even number. (if you put byte 0, 2, 4, 6 it is fine. If you put 1, 3, 5, 7 you will see it go to 0, 2, 4, 6).
  • Our team is fixing this issue, and the fix will be available in Quartus v24.3.1 in few month later (subject to change)
  • At the same time, we are filling a FPGA knowledge based article to inform other user about this behavior. Pending to be available within 1-2 weeks.

At the meantime, To ensure that the entered byte location is correctly assigned, please verify that in the table showed in DPHY IP / IP Configuration tab Enabled Links section shows the desired byte location for each enabled Link.

Hope this is clarified and work for you. Let me know if you have any further question.

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.