Agilex5 mipi phy IP configuration issue

Hi,

If we assign odd bytes and attempt to compile, it results into signal connection errors. No such error is seen for even byte assignment
>> if you refer to our user guide under 4.1. Identifying Pin Assignments Based on Byte Location
>> MIPI D-PHY design using 2 data lanes and 1 clock lane assigned to byte location 7
>> Hence, the scenario you seeing is expected.

If we assign odd bytes and attempt to compile, it results into signal connection errors. No such error is seen for even byte assignment
>> you may need to assign the remaining unused pin to prevent the error
>> 4.4. Using the Remaining I/O Pin from Same Byte Location

Hope that clarified ,

Regards,
Wincent_Intel