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alexislms's avatar
alexislms
Icon for Contributor rankContributor
3 years ago
Solved

Agilex "support logic" gives failed synthesis rules with medium severity

The Agilex's support logic gives failed synthesis rules with medium severity. RES-30133 - Embedded Memory Blocks with Initialized Content That Might be Modified Before the FPGA Enters User ...
  • ShengN_altera's avatar
    ShengN_altera
    3 years ago

    Hi,

    Below are the messages from internal:

    This is a false warning. It has been reported multiple times already. We are working with the Design Assistant team to suppress it, but we are not going to change the SRC to try to remove it.

    I am working with the Design Assistant team to provide a way to disable this error in the SRC RTL. Right now, this cannot be done.

    Check the attached picture. Can just ignore them for now.

    Thanks,

    Best regards,

    Sheng

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

Below are the messages from internal:

This is a false warning. It has been reported multiple times already. We are working with the Design Assistant team to suppress it, but we are not going to change the SRC to try to remove it.

I am working with the Design Assistant team to provide a way to disable this error in the SRC RTL. Right now, this cannot be done.

Check the attached picture. Can just ignore them for now.

Thanks,

Best regards,

Sheng