Forum Discussion

brian1211's avatar
brian1211
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Agilex EMIF error 14566?

I get a similar error on the same data pin on a 2nd EMIF instance. It appears the pinout follows all the requirements but still getting the errors below: Error(14566): The Fitter cannot place 2 p...
brian1211's avatar
brian1211
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Adzim,

According to the "Intel Agilex FPGA EMIF IP – Product Architecture 683216 | 2022.11.03", and the agib027.xlsx for the R29A show the AGI027 in R29A package has 2A and 2D not bonded. 2B, 2E, 2F, and 2C are bonded. Is that not accurate? And according to my tripled verification of the pins used, we are using 2F for data, and 2C for address and command. Can you give an example pin that is in bank 2D?

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Brian,

That is accurate. What I mean is the connection between the IO Bank 2C and IO Bank 2D is not bonded.

I will attach the example design in .qar file.

  • brian1211's avatar
    brian1211
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Adzim,

    I see the updated qsf from your *.qar file, but I don't understand what is wrong with the pinout we used. The banks and IO lanes used are the same just different DQ/DQS groups are in different locations. What rule is being violated?

    Thanks

  • brian1211's avatar
    brian1211
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Adzim,

    In looking at the qsf from your *.qar file, there are a number of nibbles that aren't contained in a nibble, they cross the nibble boundary (they stay in the byte).

    Example:

    set_location_assignment PIN_LH42 -to emif_mem_mem_dq[71]
    set_location_assignment PIN_LL43 -to emif_mem_mem_dq[70]
    set_location_assignment PIN_LL39 -to emif_mem_mem_dq[68]
    set_location_assignment PIN_KW43 -to emif_mem_mem_dq[69]
    set_location_assignment PIN_KW41 -to emif_mem_mem_dqs_n[17]
    set_location_assignment PIN_LB40 -to emif_mem_mem_dqs[17]
    set_location_assignment PIN_MA34 -to emif_mem_mem_dqs_n[8]
    set_location_assignment PIN_LW33 -to emif_mem_mem_dqs[8]
    set_location_assignment PIN_KW39 -to emif_mem_mem_dq[65]
    set_location_assignment PIN_LB38 -to emif_mem_mem_dq[64]
    set_location_assignment PIN_LB42 -to emif_mem_mem_dq[66]
    set_location_assignment PIN_LH38 -to emif_mem_mem_dq[67]

    LL39 is in DQ44, while LH42, LL43, and KW43 are in DQ45.

    How did you generate this pinout for the EMIF? And what is wrong with the one we generated? If I don't know what is wrong I can't fix it on other EMIF interfaces.