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brian1211's avatar
brian1211
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Agilex EMIF DDR4 LRDIMM 4 rank Address/command placement?

What is the required pin placement in the address/cmd subbank for a DDR4 LRDIMM with 4 ranks. The table: https://www.intel.com/content/www/us/en/content-details/655987/external-memory-interface-em...
brian1211's avatar
brian1211
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Using Scheme 1A should the CS_N_2 and CS_N_3 be put in the same place as for Scheme 1? Lane 3 index 0 and 1.

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Yes put it in Lane 3 index 0 and 1.