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xiaohao's avatar
xiaohao
Icon for New Contributor rankNew Contributor
5 months ago
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agilex 7 Platform Designer PIO 2x8

I used the Platform Designer PIO 2x8 example to build my own setup, but when I run lspci on the computer, I can only see one device pcie1, and cannot see pcie0. My hardware connections should be fine...
Pcie
  • VenT_Altera's avatar
    VenT_Altera
    5 months ago

    Hi xiaohao 

    Thank you for your updates. 

    Please generate the PIO Gen4 x8x8 design example directly from the P-Tile AVST IP Parameter in Quartus. These configurations are supported for your use case:

    • Gen4 x8x8 512-bit (250 MHz or below) Endpoint
    • Gen4 x8x8 256-bit Endpoint

     

    This design example only supports the default settings in the Parameter Editor of the P-tile Avalon Streaming IP for PCI Express. Therefore, leave all parameters at their defaults and modify only:

    • Hard IP Mode
    • PLD Clock Frequency

     

    After that, click “Generate Example Design.”

    Refer to P-Tile AVST Design Example User Guide: https://docs.altera.com/r/docs/683038/24.1/p-tile-avalon-streaming-ip-for-pci-express-design-example-userguide/directory-structure 

    Please let me know if you have any concerns.

    Thanks. 
    Best Regards,
    Ven 

xiaohao's avatar
xiaohao
Icon for New Contributor rankNew Contributor
5 months ago

Thank you very much for your reply. I realize I should check the relevant settings in the BIOS. The documentation you provided seems rather complex and offers limited practical guidance for my specific use case, as I have little prior experience in this area.

Regarding another issue: I am working with a custom-designed FPGA board using the AGFB027R25A2E2V chip. I have successfully implemented and run the PIO example project for intel_pcie_ptile_ast_0 Gen4 x16. However, when attempting to configure a 2x8 PIO setup, I encounter an issue where only one link is recognized by the system. Within the Quartus tool, I have been unable to locate a dedicated example project for a PIO 2x8 configuration. My initial attempt resulted in failure (the tool generated an x16 configuration instead). Would it be possible for you to share a reference example project for the 2x8 PIO implementation?

VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
5 months ago

Hi xiaohao 

Thank you for your updates. 

Please generate the PIO Gen4 x8x8 design example directly from the P-Tile AVST IP Parameter in Quartus. These configurations are supported for your use case:

  • Gen4 x8x8 512-bit (250 MHz or below) Endpoint
  • Gen4 x8x8 256-bit Endpoint

 

This design example only supports the default settings in the Parameter Editor of the P-tile Avalon Streaming IP for PCI Express. Therefore, leave all parameters at their defaults and modify only:

  • Hard IP Mode
  • PLD Clock Frequency

 

After that, click “Generate Example Design.”

Refer to P-Tile AVST Design Example User Guide: https://docs.altera.com/r/docs/683038/24.1/p-tile-avalon-streaming-ip-for-pci-express-design-example-userguide/directory-structure 

Please let me know if you have any concerns.

Thanks. 
Best Regards,
Ven