agilex 7 Platform Designer PIO 2x8

Hi xiaohao 

Thank you for your updates. 

Please generate the PIO Gen4 x8x8 design example directly from the P-Tile AVST IP Parameter in Quartus. These configurations are supported for your use case:

• Gen4 x8x8 512-bit (250 MHz or below) Endpoint
• Gen4 x8x8 256-bit Endpoint

This design example only supports the default settings in the Parameter Editor of the P-tile Avalon Streaming IP for PCI Express. Therefore, leave all parameters at their defaults and modify only:

• Hard IP Mode
• PLD Clock Frequency

After that, click “Generate Example Design.”

Refer to P-Tile AVST Design Example User Guide: https://docs.altera.com/r/docs/683038/24.1/p-tile-avalon-streaming-ip-for-pci-express-design-example-userguide/directory-structure 

Please let me know if you have any concerns.

Thanks. 
Best Regards,
Ven