Agilex-7 MSI-X missing om AXI MCDMA for PCIe

Hi Mikhail_a ,

I lay down some document, Hope it can help you to move forward

5.4.8. User Event MSI-X Interface

https://docs.altera.com/r/docs/817911/25.3.1/axi-multichannel-dma-ip-for-pci-express-user-guide/user-event-msi-x-user_msix

9. Registers

https://docs.altera.com/r/docs/683821/25.3.1/multi-channel-dma-ip-for-pci-express-user-guide/registers

https://docs.altera.com/r/docs/683821/25.3.1/multi-channel-dma-ip-for-pci-express-user-guide/control-registers

The address range for the MSI-X Table and PBA is within the configuration, control and status registers: 0x10_0000 – 0x1F_FFFF

I'm still interested if I need to enable MCDMA somehow so it can handle MSI-X requests. Because from MCDMA control registers description it is not that obvious if we need to do something for MSI-X to be sent. 
>> If you configure the IP core to have 1 DMA channel, the table has 4 entries, where each entry is 4 DWORDs, 1 entry for each H2D/D2H DMA/User Event vector.
>> I actually think this is somewhat best explained in our MACsec System Design User Guide - our MACsec IP utilizes the MCDMA IP, but needs to send its own MSI-X interrupts using the exact same user interrupts you are trying to use.

Please refer to section 2.6. Interrupts

https://docs.altera.com/r/docs/767516/23.4/macsec-system-design-user-guide/interrupts

Regards,
Wincent