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jaime_e-space's avatar
jaime_e-space
Icon for New Contributor rankNew Contributor
5 months ago

Agilex 7 LVDS SERDES IP : Wrong behavior in simulation (coreclock too slow)

Hello, I've been trying to simulate the LVDS SERDES IP (6-bit) on my design with Questa Intel FE, and it looks like there is something weird with the coreclock output (both in TX and RX). I see the...
Jesd
Farabi's avatar
Farabi
Icon for Regular Contributor rankRegular Contributor
4 months ago

Hello Jaimie,


I am taking over this case from previous owner.


From the information you provided, the coreclk remains high for much longer than expected. This caused input samples to be skipped, resulting in repeated serialization of the same input word.

Can you observed the PLL is locked all the time during the transition?


regards,

Farabi




  • jaime_e-space's avatar
    jaime_e-space
    Icon for New Contributor rankNew Contributor
    4 months ago

    Hello Farabi,

    At the end I found the solution. The simulation doesn't accept to start with an asserted reset. Instead, if I toggle the reset, the right behavior is found...

    Regards

    Jaime