Forum Discussion
Agilex-7 AXI MCDMA for PCIe hang
Hi VenT_Altera ,
My setup looks next way:
I've generated example design with traffic generator and then substituted traffic generetor with my own simple TG that can send arbitrary number of bytes.
So general structure and IPs connection comes from example design except traffic generator.
I can send you screenshots of settings window of both PCIe related IPs. But generally it is almost the same as in files i've send at the begining.
I can setup signaltap signals to any you may need, run the test and send you results.
Thanks,
Mikhail
- VenT_Altera28 days ago
Frequent Contributor
Hi Mikhail_a,
Thanks for the detailed description. Based on what you've shared, the following points are very likely contributing to the hang you're observing with 449-byte payloads in your BAS-based custom TG.
1. BAS Address/Payload Alignment Requirement
With your Gen4 x16 configuration, the AXI-MM data width is 512 bits (64 bytes). The Bursting Slave's addresses must be aligned to the width of the data bus — for example, if the data width is 64B, the addresses must align to 64B.
449 bytes is not a multiple of 64 bytes, which immediately violates this constraint. Your custom TG needs to ensure that both the start address and the transfer length are 64-byte aligned for the BAS interface at Gen4 x16 (512-bit data width).
Note that, in the design example, the burst size is set to 256 bytes. Therefore the BAS transfer size must be a multiple of 256 bytes.
2. "Enable Address Byte Aligned Transfer" Is Not Supported
The "Enable address byte aligned transfer" option has a value of Off and default of Off — this option is not supported in the current release. AXI Multichannel DMA IP for PCI Express* User Guide There is a documented known issue associated with this: when address byte aligned transfers are enabled, a DMA failure may be observed for lower payload sizes on the AXI interface. Byte aligned access is not supported — address should be aligned to the data width.
So even if you were to attempt byte-aligned operation, the IP doesn't support it, and using non-aligned transfers risks exactly the DMA failure / hang you're seeing.
You may round your custom TG's transfer sizes up to the nearest 64-byte boundary (e.g., 449 → 512 bytes), and ensure the start address is also 64-byte aligned.
If you can set up SignalTap on the BAS write address channel (
bas_axi_mm_awaddr,bas_axi_mm_awvalid,bas_axi_mm_awready,bas_axi_mm_awlen) and the write response channel (bas_axi_mm_bvalid,bas_axi_mm_bresp), that would confirm whether the hang occurs at address acceptance or at the write response phase. But fixing the alignment to 64B first is the most direct next step.Thanks.
Best Regards,
Ven
- Mikhail_a26 days ago
Occasional Contributor
Hi VenT_Altera
Thank you for your reply. I've run some experiments and took screenshoots from signaltap
All writes burst start from address 0xFFFC0000 - so it is 64 bytes aligned in every case. Below there are different bursts for differend data length in bytes.
448 - no server hang
400 - no server hang
399 - no server hang
459 - no server hang
449 - instant server hang
So you see that in that case only 64 bytes aligned address was used and even when wstrb is not all ones write transaction may not cause server hang. Only particular data size like 449, 450, 451 bytes cause server hang, while 559 cause no problems.
Best regards,
Mikhail