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Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
3 months ago
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AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0]

Hello, In AGILEX 5E : GTS AXI Streaming IP for PCI Express user guide : ug-813754-855610.pdf What is the mapping of the PCIe Header on "_tuser_hdr[255:0]" signal when the PCIe0/1 AXI-ST Sideband H...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 months ago

    Hi @Serge93 ,

    The header format for inband and sideband is the same, thus we do not have a separate set of definition for sideband header.
    We will include this information more explicit in our next IP UG version.

    Regards,
    Wincent_Altera

Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

Hello Wincent,

Thank you for your answer but I meant the detail mapping as the following picture for Tdata :

Do you have the same for the _tuser_hdr[255:0] signals ?

Thank you.
Serge

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 months ago

Hi @Serge93 ,

The header format for inband and sideband is the same, thus we do not have a separate set of definition for sideband header.
We will include this information more explicit in our next IP UG version.

Regards,
Wincent_Altera

  • Serge93's avatar
    Serge93
    Icon for Occasional Contributor rankOccasional Contributor
    3 months ago

    Thank you Wincent.

    Serge

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 months ago

      Hi Serge,

      You are most welcome, if you have any question please do file a new forum thread.
      We will be there to ensure your success.

      Regards,

      Wincent_Altera