Forum Discussion
ContributorAgilex 5 GTS PMA/FEC Direct Loopback
Hi,
Thanks for your update.
Based on your description, it seems your datapath is structured as follows:
Oscillator → tx_parallel_data input → GTS PHY → rx_parallel_data output → DMA → HPS
To achieve this setup, you can enable the Parallel Loopback path (Path B). This configuration allows the parallel data fed into the TX interface to be directly routed to the RX interface, bypassing the serializer, deserializer, and CDR blocks.
This approach should help simplify your testing or validation process without involving the full high-speed serial path.
Let me know if you need further clarification or assistance.
Best regards,
Chee Pin
Regular ContributorHi,
I understand you have some inquiries regarding the parallel loopback configuration of the XCVR PHY. To ensure we're aligned, could you kindly elaborate on the specific data flow of your target implementation?
It would be helpful if you could reference Figure 21: PMA Loopback Modes in the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs, so we can better understand your intended setup and provide more accurate guidance.
Looking forward to your clarification.
ContributorYes let me explain a little more.
My design will be:
Oscillator -> GTS (loopback) -> DMA -> HPS.
Where the oscillator produced parallel data, the GTS serialises it and loops it back deserialised, and the DMA fetches data for a user application.
I really don't have a preference in terms of what loopback mode to use, it could be any of the three - likely I will try them all.
Many thanks!
