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Hi, I am a few months in to building a data acquisition system on a DE1 board (for prototyping) and have written a FIR filter using VHDL. I have noticed that Altera provides the megafunctions for FIR filters at about $4000 per license. I have also noticed that my filter gobbles up quite a bit of adder-multipliers...(I need to filter signals for a neuroscience application so they range from 1Hz to 6kHz). Ideally I would like to have 32 parallel and re-loadable filters in this project. I would prefer to obviously maximize the sharpness of the filter, which will drive the number of taps up at the cost of space on the cyclone II.
Does anyone know what would be the most cost effective way to cut down on adder-multipliers...? would the altera IP help, or are there more slick alternatives to managing resources without breaking the bank? I would really appreciate help with this :D
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There are plenty of plans & tricks.
1) consider IIR
2) consider averaging filter
3) resource reuse if your clock is much faster than signal rate
4) exploit symmetry,power of 2, multiple additions, and so on.
It depends and you need to describe your filtering in more details
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