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Altera_Forum
Honored Contributor
Honored ContributorAccumulator in IP and RTL timing errors
Hello, I've implemented accumulator that computes the sum of 19-bit incoming data samples magnitudes for particular period of time to 33-bit bus. I use RTL: always @ (posedge clk) if (frame)...
Altera_ForumHonored Contributor
Honored ContributorAgreed. If we take the setup error of -14ns as being correct (ie, the logic path you have really does take 8.2ns+14ns = 22.2ns) then having FRAME asserted every other clock is still not sufficient. It takes a minimum of three clock cycles (ie, 3x8.2ns = 24.6ns > 22.2ns) to compute and have a positive setup time (24.6-22.2 = +2.4ns).
