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Altera_Forum
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9 years ago

Accumulator in IP and RTL timing errors

Hello, I've implemented accumulator that computes the sum of 19-bit incoming data samples magnitudes for particular period of time to 33-bit bus. I use RTL: always @ (posedge clk) if (frame)...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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I've tried it. It still give me the same -14 ns error at the accumulator output.

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That can't be right. You have either applied multicycle to another path or your constraint is ignored.