Forum Discussion

Honored Contributor

9 years ago

Accumulator in IP and RTL timing errors

Hello, I've implemented accumulator that computes the sum of 19-bit incoming data samples magnitudes for particular period of time to 33-bit bus. I use RTL: always @ (posedge clk) if (frame)...

Altera_Forum

Honored Contributor

9 years ago

you can also apply a setup multicycle of 2 (hold of 1) to paths fom sqrt to accum and from accum to accum(as it is under frame enable)

Forum Discussion

Accumulator in IP and RTL timing errors

Recent Discussions

Agilex 7 slew rate reconfiguration

Agilex-7 AXI MCDMA for PCIe hang

Constraints not being picked for DCFIFO

Can't generate F-Tile Ethernet Hard IP Design Example

MAX10 TSE reference design