Accumulator in IP and RTL timing errors

Are the registers for 'frame' and 'magnitude' operating in the exact same clock domain (ie, clocked from @(posedge clk) )?

Is the output port of ALTSQRT that 'magnitude' comes from registered on @(posedge clk) ?

A 122MHz clock rate is a period of 8.2ns. A 14ns setup error says that the clock period needs to be 22.2ns minimum, or about 45MHz Fmax.

I would try registering the output of ALTSQRT into 'magnitude' on @(posedge clk) just to see how that works.

You don't explicitly say the width of 'accum' but I am inferring it is 33 bits. I would think that device can do a 33b add in 8.2ns or less.