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Altera_Forum
Honored Contributor
Honored ContributorAccumulator in IP and RTL timing errors
Hello, I've implemented accumulator that computes the sum of 19-bit incoming data samples magnitudes for particular period of time to 33-bit bus. I use RTL: always @ (posedge clk) if (frame)...
Altera_ForumHonored Contributor
Honored ContributorTiming error(s) on what path?
Where do the inputs 'frame' and 'magnitude' come from (another register or device input pins)? Will make a big difference on timing.
