About timing of signal BUSY in Altera ASMI Parallel IP Core

Hi,

You can use both of these condition.

However, my strongly recommendation for sampling the busy signal is Busy signal goes to '1' on rising edge of clkin and Busy signal goes to '0' on falling edge of clkin.

In addition, when the busy signal goes to ‘0’, please allow two clock cycles before sending a new signal.

Thanks.😉 😉