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Altera_Forum's avatar
Altera_Forum
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16 years ago

about the signal of "ff_rx_dsav"

Hi,

when I simulated the Triple speed ethernet MAC,I added a data interface contro module to the mac,I found the signal ff_rx_data[7:0] have data stream out,but there are serval "00" bytes in the stream and the signal ff_rx_dsav was deasserted and rx_err[5:0]=6'b000110,how does that happen?

I set the mac interface register as following:

register offsetregister namevalue0x08command_config0x0080_00330x04scratch0xAAAAAAAA0x0Cmac_00x17231C00

0x10mac_10x0000CB4A

0x14

frame_length

0x5ee

0x18

pause_quant

0x0f

0x1C

RX_section_empty

0x10

0x20

RX_section_full

0x10

0x24

TX_section_empty

0x100x28

TX_section_full

0x10

0x2C

RX_almost_empty

0x08

0x30

RX_almost_full

0x08

0x34

TX_almost_empty

0x08

0x38

TX_almost_full

0x0A

ox3c 0x00

0x5c 0x0c

0xe8 0x00

0xec 0x00

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    What are you sending on the MII side? The error word that you get seems to indicate "CRC error" and "Invalid frame length"

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi,

    Thank you for your reply!

    Firstly,I added data stream to "ff_tx_data",then the gm_tx_d[7:0] have data out.

    secondly,I copy the out data and the signal of enable to gm_tx_d[7:0] interface.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Did you create a loopback?

    Quartus creates a testbench with the TSE component. It could be a good idea to try and run it and compare with yours.