Forum Discussion
lambert_yu
Contributor
5 years agoAbout master and slave design of EMIF on arria 10
Hi all,
I face problems about master and slave design of EMIF's IPs on arria 10:
for this design case :
1) each emif_usr_clk signals from emif_master and emif_slave is always...
AdzimZM_Altera
Regular Contributor
4 years agoHi Lambert,
I put the case to closure since you already found the solution for your issue.
Feel free to file a new case if you encounter a new problem.
Regards,
Adzim