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lambert_yu's avatar
lambert_yu
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4 years ago

About master and slave design of EMIF on arria 10

Hi all, I face problems about master and slave design of EMIF's IPs on arria 10: for this design case : 1) each emif_usr_clk signals from emif_master and emif_slave is always...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Lambert,


Do you have any update on my last feedback?


Regards,

Adzim


lambert_yu's avatar
lambert_yu
Icon for Contributor rankContributor
4 years ago

Hi Adzim,

Just because the time gap got from the scope between avl_ready_s and avl_ready_m, the time gap got from the scope between avl_read_valid_s and avl_read_valid_m are all not one a fix value, so I can not privide the timing skew.

Brs,

Lambert