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lambert_yu's avatar
lambert_yu
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4 years ago

About master and slave design of EMIF on arria 10

Hi all, I face problems about master and slave design of EMIF's IPs on arria 10: for this design case : 1) each emif_usr_clk signals from emif_master and emif_slave is always...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Lambert,


Switching between read and write operation can reduce the efficiency of your controller because its needs to issue the precharge and activate commands for the operation and access the bank and row.


By the way, there are methods to improve the efficiency of your controller such as Auto-Precharge Commands, Additive Latency, Calibration and so on.

You can refer to the Arria 10 EMIF User Guide in the link below on Chapter 13.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf


But its depends on your design controller to handle the traffics of the operations.


Thanks,

Adzim


  • lambert_yu's avatar
    lambert_yu
    Icon for Contributor rankContributor
    4 years ago

    Hi Adzim,

    Is there any information for the timing skew of avl_master_ready and avl_slave_ready signals based on master and slave design of EMIF ?

    Brs,

    Lambert