Forum Discussion
lambert_yu
Contributor
5 years agoAbout master and slave design of EMIF on arria 10
Hi all,
I face problems about master and slave design of EMIF's IPs on arria 10:
for this design case :
1) each emif_usr_clk signals from emif_master and emif_slave is always...
AdzimZM_Altera
Regular Contributor
5 years agoHi Lambert,
I'm Adzim. Thanks for using the Intel Community.
May I know which memory type that you used?
Thanks,
Adzim
lambert_yu
Contributor
5 years agoHi Adzim,
I am using DDR4-2666 ( MT40A512M16LY-075), thanks.
Brs,
Lambert