About altera_a10_xcvr_clock_module, CLKUSR pin of Arria 10

Hi Lambert,

I can sense your confusion.

You are still trying to touch on "mgmt_clk".

• You don't need to do any extra connection to mgmt_clk.
• When you instantiate "altera_a10_xcvr_clock_module reset_clock(.clk_in(mgmt_clk))". It basically tell Quartus to do some internal background processing. User is not suppose to use or connect mgmt_clk to any signal (including clkusr)

Let me explain again.

(A) If you plan to use transceiver, provide on board external clock to FPGA clkusr pin

• DO NOT connect clkusr port to anything in your RTL design anymore

(B) If you don't plan to use transceiver, and plan to use clkusr pin as general input clock pin

• instantiate altera_a10_xcvr_clock_module: altera_a10_xcvr_clock_module reset_clock (.clk_in(mgmt_clk))
• You do not need to connect clkusr to mgmt_clk.
• Just use clkusr like normal input clock pin and connect to you RTL design logic.

Thanks.

Regards,

dlim