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MikeH1's avatar
MikeH1
Icon for New Contributor rankNew Contributor
4 years ago

A10 PCIe Device not seen by Windows

As shown in SigTap snapshot below, there is an extra pulse of app_nreset_status at sample 61. When this happens, the PCIe device does not enumerate correctly in Windows. I also have a dump of raw ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


May I know what is the speed and link width you are trying to achieve? Could you check if the power supply (VCCR_GXB) is set correctly in the Assignment editor and measure the power supply (VCCR_GXB) supplied to FPGA board is matched with voltage set in the design setting?


Thanks

Best regards,

KhaiY





MikeH1's avatar
MikeH1
Icon for New Contributor rankNew Contributor
4 years ago

PCIe Core mode is set to: Gen3 X2, 128bit, 125MHz

VCCR_GXB is 1.03V when measured on the board (pins J19 and J20).

I don't see where these pins (J19 and J20) are called out in the assignment editor, where are these located?

Thx.