A read memory problem via Quad SPI mode in Generic Serial Flash Interface IP

Question

Hey,
I'm using the Reference design Generic Serial Flash Interface IP on Quartus Prime 18.1 to access Micron MT25QL512Mb flash memory.
Via NIOS processor, I able to read the memory data correctly in the single SPI mode by the function:

int read_memory()
{
    IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x4,0x00000000);
    IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x0,0x00000101);
    IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x5,0x00000003);
    return            IORD(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_BASE,0x00000000);
}

But when I'm trying to read the data in Quad SPI mode, I always got x"FFFF":

int read_memory_quad()
{
    IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x4,0x00022222);
    IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x0,0x00000101);
    IOWR(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE,0x5,0x00000A0B);
    return            IORD(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_BASE,0x00000000);
}

this is the Device's datasheet (page 37):
https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_l_512_abb_0.pdf?rev=0ef0faa5f7b645d7bc11c30bfd27505b

I would like to get some help here,
Thanks

mathiasb · Answer

Hi,
From your read_memory_quad function, it seems that you are configuring the IP but not the component. For instance, you set the IP to behave as Quad IO and 4-bytes adressing, but you also need to set the registers of the component. Or do you do this in another function prior to this one?

gyud0 · Answer

I indeed configure the IP as 4-byte addressing and then read the data by read_memory_quad function (CSR region)
I don't understand the registers you are talking about.

mathiasb · Answer

I was refering to the configuration registers on page 24 of the datasheet. Don't you need to set them in order to enable Quad mode for instance?

gyud0 · Answer

Can you guide me how I have to set that thing?

mathiasb · Answer

Actually, I think you must have done it at some point, because otherwise the QSPI's register bit 0 (addressing mode) would be 3-bytes (default value) while you have configured the IP as 4-bytes. And this is also true for the first, Single IO read function: in my opinion, it should not work (I may be mistaken).

On a side note, you might not have to do all the steps below if instead of FAST READ you use the 4 BYTE QUAD (INPUT) OUTPUT FAST READ command(s).

Putting that aside, to address any configuration or status register of a QSPI with the GSFI IP, you need to use the CSR register 0x7. There is a number of fields in this register that you need to configure depending on the command you want to use:

1) you need to to a Write Enable to modify configuration register (Opcode = 0x06). You can IOWR 0x06 to register 7, for this one.

2) you need to write the configuration register itself, either with WRITE VOLATILE (Opcode = 0x81) or WRITE NON VOLATILE (Opcode = 0xB1). You need to set the number of data bytes to either 1 or 2, depending on the command, in register 7. You put the data you want to write in the 0xA/0xB registers of the IP.

3) (optionnally) if you use WRITE NON VOLATILE, the datasheet states that you need to poll the STATUS REGISTER or FLAG STATUS REGISTER until completion. That means you need to change register 7 once more according to the READ (FLAG) STATUS REGISTER Opcode. The read back data will be in the 0xC/0xD registers.

Hope it can help to solve your problem!

Forum Discussion

A read memory problem via Quad SPI mode in Generic Serial Flash Interface IP

5 Replies

Recent Discussions

PCIe Enumeration Failure for CXL IP

Can't generate F-Tile Ethernet Hard IP Design Example

Agilex 7 slew rate reconfiguration

Constraints not being picked for DCFIFO

Cyclone 10 GX IBIS-AMI models