A question about rd_usedw and wr_usedw for a DCFIFO

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I found there're 2 signals for usedwidth : rd_usedw and wr_usedw

I don't understand the difference between these two signals.

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A dual-clock FIFO has two clock domains, the write clock domain (which uses wr_usedw) and the read clock domain (which uses rd_usedw).

This is much clearer if you use Modelsim to simulate your components.

Please see this thread for a zip file containing simulations of both scfifo and dcfifo components:

http://www.alteraforum.com/forum/showthread.php?t=38988

Cheers,

Dave