64 bit Avalon MM to ST FIFO for PCIe 3.0 IP core

Hi skbeh

Thanks for your response. I am using Arria V FPGA, but I believe the example project(Avalon MM interface for PCIe with DMA) that I'm using works for both, with the exception of some Quartus settings.

The problem I have is to convert from BAR's MM interface to an ST interface which is 64 bits wide. Apparently the MM to ST FIFO can only have a 32 bit data width.

By the way, what makes you say that 64-bit data width is supported? Although I select the BAR to be 64 bits wide, after looking at its block view for signals, only the address width changes to 64 bits and the data width remains 32 bits wide. Please see the attachment.

Is a 64 bit address bus ever useful? Are we ever going to address that much memory?

Thanks

Ankit Pradhan