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Altera_Forum
Honored Contributor
Honored Contributor64 bit Avalon MM to ST FIFO for PCIe 3.0 IP core
Hello everyone I am working on integrating the PCIe3.0 IP core from Altera with my existing application. So far we have been using SFP interface to communicate with the host and we would like t...
Altera_ForumHonored Contributor
Honored ContributorI believe you are using Stratix V FPGA, correct?
Stratix V PCIe core should be able to support 64-bit data width for application layer to Transaction Layer interface.
