Honored Contributor
Honored Contributor>1, I need to include a pattern generator/checker. >But the xgmii sdr interface is one 72-bit >symbol/beat, while the ST
I don't quite understand your problem. But hopefully some information may help. Regarding this item, the 72 bit is consisting of 64-bit data (bit 63:0), and 8 bit control. Break the 64 bit into 4x16 bit chunks, then you can use the test pattern design example from Altera (looks like you have this already) with some modifications by configuring their 10bit design into 16 bit. You need to use the 4 channel version to get 64 bits. You need to change the timing adapter and data adapter in the design example to match the outputs/inputs from your Transceiver. This can be done in Qsys, and Edit the instantiation to 2 symbol per beat (times 4 of course). Hope that helps.
