100G Ethernet IP (Stratix 10) does not complete placement

Hi @JMiret

I am Richard Tan and get to know that you need help in regards to the fitter issue.

From the discussion:

The errors 170078 indicate that the compiler had difficulties finding a legal placement solution for the design. This may be caused by invalid location assignments, conflicting assignments, assigning nodes to incompatible physical locations on the device, not enough resources or hard-to-place Logic Lock regions.

Action: Try to remove any invalid or conflicting assignments for the node. Also refer to the Fitter Floorplan view for overfilled regions on the device.

Whereas errors 170079 may be caused by not having enough resources or by hard-to-place Logic Lock regions that can interfere with the placement of this node.

Action: Try to choose a different seed value in Fitter Settings. If the design has Logic Lock regions, you can try to modify some of the Logic Lock regions.

Have you try to run the design in our latest Quartus version 21.2 and see if the issue still persist?

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.