100G Ethernet IP (Stratix 10) does not complete placement

Hi,

Based on all your explanation so far + the symptom that SAME design sometime passed fitter compilation, sometime failed fitter compilation

• I suspect this is likely due to your selected FPGA device core logic resource congestion issue
• Then this has nothing to do with Ethernet IP functionality nor the Ethernet design itself, right ?
• Sometime SDC constraint will affect the fitter placement result as well depends on how you constraint the clock/move the logic placement around.

You said that by creating smaller scale of design then it can passed fitter successfully, right ?

• You can try debug experiment like use back your bigger design but purposely change to bigger FPGA device to test the fitter compilation. If fitter passed then you can be sure this is resource logic congestion issue
• You can also view the Quartus "chip planner" in fitter passing design to see if your design is all concentrated in certain area of your FPGA device

Initially I pick up this case support due to we thought the issue is with Ethernet IP but now since this is related more on fitter compilation debug, then I will consult Intel internal team to see if I can get our Quartus software support agent to advise you further on fitter debug.

Thanks.

Regards,

dlim