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TYasu8's avatar
TYasu8
Icon for New Contributor rankNew Contributor
6 years ago

ノイズ対策　入力端子

入力端子に、矩形波で3500Hzと20Hzがそれぞれ別の入力設定のピンから入力されます。下記のようなクロック2回分連続で入力されたら正規の信号とするようなもので対応しています。 もっと効果的なFPGAの設定やIP(DSPのFIRフィルタは使えますか？)が有りましたら教えて下さい。宜しくお願いします。​ proc_clk: PROCESS (clock) BEGIN IF clock'...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

As I understand it, you have some inquiries related to DSP design implementation. For your information, generally we only address specific inquiries related to FPGA or IP but not design implementation which would more toward design service. Hope you could understand it. However, I will try my best to address to my best knowledge. Sorry as I am not very clear about your target implementation. Would you mind to further elaborate on it? Some illustration would be helpful for better understanding.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin