Yet another Timing Constraints question

I'm working on a project (for fun) that involves an EP3C25, the TG68 softcore and a Winbond W9825G6JH SDRAM. I'm trying to get the RAM properly constrained, but I must be doing something wrong, because whether or not the project passes IO timing and whether or not the project *works* seem to be completely unconnected!

I have a PLL generating two clocks - c0 => master clock at 113.5MHz and c1 => SDRAM clock at the same frequency with a -2ns phase shift. (Picked to optimise slack according to TimeQuest) The board in question is wired such that I can't use dedicated routing for the SDRAM clock, but I've got fast output (and input) enabled for all the SDRAM related pins.

I've used the instructions in the document "Constraining SOPC Designs V1.1" as a starting point, so here's what I've got so far.

The SDRAM has a COA of 5.4ns, output data hold time of 3ns,

command/data/address setup time of 1.5ns and command/data/address hold time of 1.0

#  Clock constraints#  Input clock
create_clock -name "clk8" -period 125.000ns  -waveform {0.000 62.500}
#  Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
set sdram_genclk {pllInstance|altpll_component|auto_generated|wire_pll1_clk}
create_generated_clock -name sdram_clk_pin -source $sdram_genclk 
# **************************************************************#  Set Clock Uncertainty# **************************************************************
derive_clock_uncertainty;
# **************************************************************#  Set Input Delay# **************************************************************
#  Not sure what board delay should be, but the board itself is very small#  so these are probably conservative estimates for combined clock and signal delay.
set_input_delay -clock sdram_clk_pin -max  
set_input_delay -clock sdram_clk_pin -min  
# **************************************************************#  Set Output Delay# **************************************************************
set_output_delay -clock sdram_clk_pin -max  
set_output_delay -clock sdram_clk_pin -min  
#  Multicycles#  without these, TimeQuest shoots for the wrong edge, due to the phase-shifted SDRAM clock.
set_multicycle_path -from {sd_data
} -to {TG68Test:mytg68test|sdram:mysdram|vga_data
} -setup -end 2
set_multicycle_path -from {sd_data
} -to {TG68Test:mytg68test|sdram:mysdram|sdata_reg
} -setup -end 2

Does anyone see anything obviously wrong there?

The generated clock on sdram_clk_pin should automatically track the phase-shift of the PLL tap, yes?

Am I right in thinking that over-estimating set-input-delay -max and underestimating set-input-delay -min makes the timing more restrictive?

Likewise, increasing set_output_delay -max and decreasing set_output-delay -min makes the timing more restrictive?

Any help would be much appreciated :)