Occasional Contributor
Occasional ContributorHi,
I'd recommend for to instantiate all the parts manually.
Yes, that seems correct.
I'll keep the case open no worries.
Regards,
Harsh M
Occasional ContributorHello Harsh,
I just noticed this quote from the ug_arria10_xcvr_phy-683617-666805.pdf document:
In my design, CLKUSR (100MHZ) is always stable before the FPGA is configured.
However, the JESD reference clock input to the PLL in the transceiver bank is sourced by the ADC.
The ADC is only configured AFTER the FPGA is configured, since FPGA logic is used to master the ADC SPI bus.
So, is this quote from the document above a hard requirement?
If it is, then I would have find a way to configure twice.
The first would enable the ADC clock output, and the second configuration cycle would be the one where transceiver does it's calibration.
Thanks
David
