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David32's avatar
David32
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

XCVR Reset Controller

We are using an Arria 10 device, 10AS057N2F40E2SG, with some JESD204 Receive only channels. The ADC being used is the T.I. ADC09QJ800AAV in JMODE = 2 (for 4 lanes, 8b/10b). I have a XCVR reset cont...
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Harshx's avatar
Harshx
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi,
I'd recommend for to instantiate all the parts manually.
Yes, that seems correct.
I'll keep the case open no worries.
Regards,
Harsh M

  • David32's avatar
    David32
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hello Harsh,

    I just noticed this quote from the ug_arria10_xcvr_phy-683617-666805.pdf document:

    In my design, CLKUSR (100MHZ) is always stable before the FPGA is configured.

    However, the JESD reference clock input to the PLL in the transceiver bank is sourced by the ADC.

    The ADC is only configured AFTER the FPGA is configured, since FPGA logic is used to master the ADC SPI bus.

    So, is this quote from the document above a hard requirement?

    If it is, then I would have find a way to configure twice.

    The first would enable the ADC clock output, and the second configuration cycle would be the one where transceiver does it's calibration.

    Thanks

    David