XCVR Reset Controller

Hi Harsh,

I took a quick look at the project linked.

That is a transmitter only, whereas I am using receiver only.

But that did give me an idea, i.e. of making a design with the bare bones receiver and only once that is working, continue on to full JESD.

Would you recommend for to instantiate all the parts manually (such as the TX PHY, TX PHY Reset controller, etc ) and individually or does some top level wrapper already exist?

In my original design (using the above-mentioned ADC from T.I.) each ADC part outputs a low-jitter replica of the internal sampling clock. This clock then forms the reference clock input to the JESD receiver / PLL.

In the bare PHY test that I will do, I assume that the correct PLL to use it the ATX PLL. Is this correct?

Thanks

David