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Altera_Forum's avatar
Altera_Forum
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12 years ago

XAUI IP Core compilation problem

Hi, I am designing a state machine to send a UDP packet through XAUI. The packet will be divided into 72 bits and reach a XAUI PHY IP Core produced by Megafunction. So basically it is not so compl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The negative pins should automatically be connected - providing you have constrained your design correctly. This includes specifying the relevant I/O standards for all the pins in the design. When you specify a differential I/O standard for a pin and assign a pin location (to the positive driver/receiver), Quartus will automatically assign the negative pin for you.

So, I suspect you've not specified a differential I/O standard for the pins you've listed.