Altera_Forum
Honored Contributor
16 years agoWrong value from 7 segment display
Hello, I am a newbie here using Cyclone II FPGA starter dev board. I am trying to program (VHDL) the 7-segment displays on the FPGA starter board to display 4 digits value. Therefore the result is not what I want and it is weird. Can anybody help? Thankyou~
Code: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY test IS PORT( HEX0,HEX1,HEX2,HEX3 :OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); end test; architecture Behavior of test is begin HEX0 <="0001000" ; HEX1 <="0001000" ; HEX2 <="0001000" ; HEX3 <="0001000" ; END Behavior; the result is weird, "0010000" "0000000" "0000000" "0000000" respectively.:confused: