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Altera_Forum's avatar
Altera_Forum
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11 years ago

Writing to HPS-DDR3 memory

Hi,

I want to use the hps_ddr_write_example design from critical link (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/writing_to_hps_memory) and test it on Arrow Terasic Cyclone V SOCKit .

I have changed the device and the HPS DDR3 parameters in the Quartus project.Also I'm using the Arrow kit's DDR3 pin assignments for the proper pin mapping.

I'm having problem with generating the Device tree for this project. There seems to be problem with the .sopcinfo file. I'm assuming since the hardware is changed I have to regenerate the software part.I have regenerated preloader and uboot.

Can anyone help me on the same?I'm new to OS porting and linux.

Thanks,

Vidya

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi Florian,

    Thanks for the reply. I'm using a project different from GHRD for the SOCKit board and I have changed the project to work on SOCKit board. Since the HPS DDR is changed, I had to generate a new preloader file. For generating .dtb file I'm using the new .sopcinfo file and GHRD provided board_info file.

    My problem is every time type this command as mentioned in rocketboards:

    sopc2dts --input mityarm_5csx_dev_board.sopcinfo\ --output socfpga.dtb\ --type dtb\ --board soc_system_board_info.xml\

    The shell gives out the description of the sopc2dts command starting from :

    sopc2dts -0.3

    Usage : sopc2dts <arguments> etc..

    When I open the .sopc file with the Sopc2dts GUI the loading file gives me this error:sopcinfo:Loading done

    Failed to find f2h_reset

    Failed to find f2h_axi_clock

    Failed to find f2h

    Can you tell me what I'm missing here.I'm not able to figure out.

    Thanks and Regards,

    Vidya