Writing the .sdc to the SoC, anything particular? Can't close timing.

Hello, tell me please, how many hardware memory channels ddr3 can be organized in the chip 5CSEMA6U23I7? I need HPS to work through the first "Hard Memory Controller and Hard Memory PHY", and the FPGA was working through the second "Hard Memory Controller and Hard Memory PHY". Each memory channel uses two ddr3 chips, with a total data bus of 32 bits. Can both interfaces work independently? Can both interfaces operate at the maximum possible frequency for the 5CSEMA6U23I7 chip at 400MHz, provided the "Enable Hard External Memory Interface" checkbox is set?