write to segment (multiple locations) of memory

Hi,

memory blocks are -as you certainly know - are ASIC like memory structures within fpgas accessible to logic through their ports and configurable through megawizard or code... into rams or roms or fifos or shift function.

I don't know what you mean exactly by memory block as opposed to these blocks. a ram has access through its ports, so is the rom and so is fifo or shift function.

You will need to click on megawizard (tool menu) and choose memory compiler then choose your configuration.

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Writing same value or different values does not make it any easier for ram access. There are as many ports as vendors have decided.

I believe you better use register array indexed as ram

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[1]

You are right if you consider the M9K, M144K to be RAMs. Somehow I thought these are generic memory blocks that can implement various types of memory: random access, FIFO, etc.

[2]

What is the most detailed information about the M9K (and the like) memory blocks available? I have the stratix iv hanbook (http://www.altera.com/literature/hb/stratix-iv/stratix4_handbook.pdf) (chapter 3), but it still does not answer all my questions.

[QUESTION I STILL HAVE]

1. How do I write VHDL code to tell Quartus tools to put a certain memory into a M9K, or M144K, or other block?

Writing same value or different values does not make it any easier for ram access. There are as many ports as vendors have decided.

I believe you better use register array indexed as ram

I think what I need is simpler than a "many port RAM".

I don't need to read multiple values in parallel. One at a time is fine.

I don't want to write different values in parallel.

I want to write one value in multiple locations (segment) by selecting the respective memory words and putting one data value on the data lines.

If I do it with registers, it's bigger in size because it gives me access to every bit of every word in parallel. I don't need that. Just write a value in multiple locations.

if you just want 128 locations then you can do that readily in registers addressed as memory table.

stratix 4 may have some 80k registers or so. so 128 x 8 means just over 1%

If you go for ram then you need very wide ram with say just 2 locations but you may need to insert registers for input/output data due to speed issues in which case you better just use registers on their own.

You can also put your values on wires (no registers, based on logic but may violate timing).

You just described a "many port" RAM which doesn't exist as dedicated hardware in an FPGA (highest I've ever heard of is 6/8 port memory but that's in the ASIC space).

You can mimic this by using a bunch of little memories but by the sounds of how many locations you want to access at once that might not be practical for your design. You could use the memory in a wider mode so that multiple byte lanes get accessed concurrently. For example for a 128x8 you could use a 256x32 M9K in true dual port mode and write 8 byte lanes all in one shot. Then duplicate the memory to span the depth you want...... again this is going to become expensive.

Do you need the writes to complete in a single cycle? A simple DMA type of engine could be used to write the same value sweeping from a start address. You won't be able to access all the addresses in one clock cycle but this would be way cheaper than trying to implement a many port on-chip memory.

The alternative is to build this out of registers to mimic having many ports. You would treat each 8-bit register as a memory location and so your write enable would be just the clock enable of the flipflop. You would need some deep muxing logic to read a value out of your memory since it would be an 8-bit mux with 128 inputs per bit so you would have to pipeline that to get some decent speed out of it.

its not as simple as what you want. What you want to do is not possible. The max D word width for M9K is 36 bit iirc, and 72 or 144bit for M144k.

You could try muxing your words eg. have a 32 bit dword, with the least sig. bits of the adderss as byte select, and then you can write 4x8bit words at once.

OK. I've played a bit with the Megafunction tool and it seems that the memory interfaces it provides are not exactly what I need.

Here is a rephrased problem statements:

Imagine you have a 128x8bit memory initialized to zero.

I want to be able to write "tail"-sections of this memory with

the same value in one clock-cycle.

Note that I always write from an index i till the end. (I call it a "tail"-section)

Example:

Write from location 64 to 127 the value 7.

Result: half memory is zero half is 7.

Write from location 96 to 127 the value 8.

Result: half memory is zero, one quarter 7, other quarter 8.

This kind of writes are trivial to implement if each memory word (location) provides a write_enable control signal, so that I could enable and disable it accordingly.

The question is how do I do in on a Stratix IV chip (EP4SGX230)?

I see that I have the following embedded memories:

• MLAB (640bit)

• M9K (9kbit)

• M144K (144kbit)

Do any of these extend the write_enable control signals for each word?

If not what is the most compact way to implement the memory I have described?

Thanks for your replies!

I will try these approaches soon, and come back with results.

And, BadOmen, GO HABS GO! (I am from the area ;)

#1 Yes they do, and often expose byte enables too depending on how you setup the memory.

# 2 I recommend using the megafunction since it'll guide you to the options that are supported. After a while you will become familiar enough that you may not need to use it anymore and can instantiate the memory directly (or just infer it).

Also I recommend going to the handbook of whatever device you plan on targeting and looking at the memory block chapter. Near the beginning of that chapter it will show you all the block types you have at your disposal and the modes they can be used in. At most you will only be able to write to two memory locations concurrently but like Kaz mentioned you can work around this limitation. Another workaround is if you know the access pattern you might be able to segment your memory into separate blocks and access multiple blocks in parallel (maybe even addresses go to block 1 and odd addresses go to block 2).